The PMS132/PMS132B single-chip microcontroller (MCU), the analog-to-digital converter (ADC) module,
The PADAUK single-chip microcontroller PMS132/PMS132B 8-bit OTP type single-chip microcontroller with 12-bit ADC.
Characteristics
General series
It is not recommended to be used in AC resistance-capacitance step-down power supply or applications with high EFT requirements. Yingguang is not responsible for not being used in such applications and not meeting safety regulations.
Working temperature range: -40 °C to 85 °C
System characteristics
• 2KW OTP program memory
• 128 bytes of data memory
• One hardware 16-bit counter
• Two 8-bit hardware PWM generators
• Three 11-bit hardware PWM generators (PWMG0, PWMG1 & PWMG2)
• Provide a hardware comparator
• Provide a 1T 8x8 hardware multiplier
• 14 IO pins with pull-up resistor options
• Each IO pin can be set with wake-up function
• Bandgap circuit provides a 1.2V reference voltage
• Up to 12 channels of 12-bit ADC, one of which comes from the internal bandgap reference voltage or 0.25 * VDD
• Provide ADC reference high voltage: external input, internal VDD, Bandgap (1.20V), 4V, 3V, 2V
• Clock source: internal high-frequency RC oscillator, internal low-frequency RC oscillator, and external crystal oscillation
• For all IOs with wake-up function, two selectable wake-up speeds are supported: normal wake-up and fast wake-up
• 8-section LVR reset setting: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
• 4 optional external interrupt pins
CPU features
• Single processing unit working mode
• Provide 87 valid instructions
• Most of them are 1T (single-cycle) instructions
• Programmable stack pointer and stack depth
• Data access supports direct and indirect addressing modes, and the data memory can be used as the data pointer (index pointer) of the indirect addressing mode
• The IO address and storage address space are mutually independent
Pin function description
The analog-to-digital converter (ADC) module. When using the ADC module, there are 7 registers that need to be configured, which are:
ADC control register (adcc)
ADC regulation control register (adcrgc)
ADC mode register (adcm)
ADC data high/low register (adcrh, adcrl)
Port A/B digital input enable registers (padier, pbdier)
The following are the steps of the ADC loading process:
(1) Configure the reference high voltage through the register adcrgc.
(2) Configure the AD conversion clock signal through the adcm register.
(3) Configure the analog input pins through the padier and pbdier registers.
(4) Select the ADC input channel through the adcc register.
(5) Enable the ADC module through the adcc register.
(6) After enabling the ADC module, delay for a period of time.
Condition 1: When using the bandgap 1.2V or 2V/3V/4V related circuits, whether it is used as the internal reference high voltage or as the AD input channel, the required delay time must be more than 1ms; if 200 AD clocks have exceeded 1ms, then the delay time only requires 200 AD clocks. When enabling the internal BG/2v/3v/4v as the reference high voltage, it must be ensured that the IHRC is in the on state.
Condition 2: Without using any bandgap 1.2V or 2V/3V/4V related circuits, the delay time only requires 200 AD clocks.
Also note: The 200 AD clocks involved in the above two conditions refer to the ADC conversion clock configured after the ADCM register rather than the system clock SYSCLK.
(7) Perform AD conversion and check whether the ADC conversion data has been completed. Set 1 to enable AD conversion and check whether adcc.6 is '1'.
(8) Read the conversion result from the ADC register:
Read the value of the adcrh register first, and then read the value of the adcrl register.
In applications, if it is to turn off the ADC module and then re-enable the ADC, or when switching the ADC reference voltage and input channel, please re-execute step 6 as above before performing the ADC conversion to ensure that the ADC module is ready.
The input requirements of AD conversion.
In order to meet the accuracy requirements of AD conversion, the capacitor's holding charge (CHOLD) must be completely charged to the level of the reference high voltage and discharged to the level of the reference low voltage. The analog input circuit model is shown in Figure 21. The signal drive source impedance (Rs) and the internal sampling switch impedance (Rss) will directly affect the time required for the capacitor CHOLD to be charged. The impedance of the internal sampling switch may change due to the ADC charging voltage; the signal drive source impedance will affect the accuracy of the analog input signal. The user must ensure the stability of the measured signal before sampling. Therefore, the maximum value of the signal drive source impedance is highly related to the frequency of the measured signal. It is recommended that at an input frequency of 500kHz, the maximum impedance value of the analog signal source should not exceed 10KΩ.
Knowledges required for the application of the output impedance of the ADC analog signal source.
Applicable scope: all single-chip microcomputers with ADC. When the external circuit outputs analog signals for ADC measurement, the issue of impedance matching must be noted, otherwise the ADC may not reach the expected accuracy. The output impedance of the external circuit must match the input impedance of the ADC pin of the chip so as not to produce measurement errors. The measured signal must reach the required accuracy before being sampled. For the extreme condition where the measured signal varies from 0V to 5V, taking the equivalent circuit where the external signal source charges and discharges the inside of the Chip as an example, as shown in the figure below.
The accuracy of its input signal can be expressed by the following formula:
If in terms of 10-bit accuracy, ∆ needs to be less than 0.001 (1/2 10); that is, the expected signal must reach more than 0.999 accuracy before being sampled.
In terms of the sampling period being 2 us, the highest period of the signal source is also 2 us, and the signal source for the charging and discharging inside the chip must have sufficient accuracy before being sampled..
The capacitance inside the chip is about 10 pF, and since the charging and discharging time of the sampling point by the ADC is only half a cycle, so T is taken as 1 us.
